This invention relates to the destructive inline testing of semiconductor gate oxides by the use of pulse voltage breakdown testing.
The inline monitoring of very thin gate oxides is a difficult, but highly desirable procedure for reducing manufacturing rejects in the semiconductor industry. Accuracy is required to ensure good chips are not wrongly rejected and defective chips are not mistakenly passed by. Accuracy, however, must be traded off against speed, so as not to hold up the production rate.
In the manufacture of semiconductor devices, various layers of material are deposited on the semiconductor substrate followed by removal of unwanted portions of each layer. The procedures used to deposit the layers, such as chemical vapor deposition in sputtering conditions, among others, as well as the procedures used to remove unwanted material, such as such as chemical, plasma, or reactive ion etching among others, may cause damage to underlying structures, particularly very thin structures, such as gate oxides.
Metal-oxide semiconductor (MOS) transistors rely upon a thin silicon oxide gate separating the gate from the channel. It is desirable to deposit these gates as thinly as possible to reduce the voltage required to activate the channel, thereby reducing the overall power requirements of the devices while simultaneously increasing their speed. Damage to the gate oxide layer may result in unacceptable current leakage from the gate to the channel, thereby resulting in reduced device performance or even total failure.
The manufacturer would therefore desire to test and monitor the gate quality of the gates coming down the assembly line so as to detect faults in the manufacturing process and to remove defective chips before further processing wasted upon them.
The current art has many procedures to test gates, some destructive, such as in electron microscopy examination wherein the wafer under examination must be cross-sectioned, and that require special circuitry be included in the wafer.
A destructive inline procedure that may or may not require additional testing circuitry on the wafer itself is pulse, or ramped voltage breakdown testing. Typically, a ramped sweep voltage is placed across the gate oxide by connecting probes to the gate and the semiconductor substrate layer, just beneath the gate oxide. A typical procedure would be to ramp the voltage from a base voltage (e.g., about 1.5 volts) to an increasingly higher stress voltage and take two current measurements, one at the base voltage and one at the stress voltage. This procedure is repeated, increasing the stress voltage each time in some small increment, usually 0.1 volts, until a maximum stress voltage is reached, usually about 7 volts. Each current measurement will generally take about 20 microseconds and there are two such measurements per ramping, so the total sweep will take at least 2*20*(7xe2x88x921.5)10.1 =2200 ins, not taking into account the time it takes for the voltage to ramp up to the stress voltage or to come back down to the base voltage. The procedure is accurate enough, but time consuming.
What is needed is a faster pulse voltage breakdown test with equal or greater accuracy than the available art.
Disclosed is a method of testing a dielectric, comprising setting a reference current below a breakdown current of the dielectric, applying a stress voltage to the dielectric below a breakdown voltage of the dielectric and measuring a stress current resulting therefrom, incrementally increasing said stress voltage until said measured stress current exceeds said reference current.